Browsing by Subject "Low Power"
Now showing items 1-4 of 4
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(2020-07-21)This project targets design of a Delta Sigma ADC with a signal bandwidth of 200MHz and an SNR of 74 dB. Reducing the power consumption in the ADC is one of the top priorities during the design phase. To achieve this, in ...
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(Texas A&M University, 2007-09-17)With shrinking feature size and growing integration density in the Deep Sub- Micron (DSM) technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. ...
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(2019-03-18)Global energy consumed by communication and information technologies is expected to increase rapidly due to continuous usage of wireless standards and the expansion for their requirements [1]. In the next generation wireless ...
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(2020-07-24)A 220 nA ultra-low quiescent bias current capacitor-less low drop-out (CL-LDO) regulator with improved single transistor control (STC) and adaptive transformation is presented in this thesis. The STC-LDO handles light load ...